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6DD1640-0AB0
O 引 言
隨著現(xiàn)
掃描控制基本流程如下：
1)程序首先計算各控制量的分段數(shù)目及段內(nèi)各控制量的起始值、步進值、步進個數(shù)。
2)通過系統(tǒng)總線，程序?qū)⑸鲜鲇嬎愫玫臄?shù)據(jù)依次送入掃描控制器內(nèi)的RAM中保存。
3)程序控制觸發(fā)單元產(chǎn)生全局中斷信號，由中斷處理單元通知運算單元讀取各控制量首段的初始值。
4)程序控制觸發(fā)單元產(chǎn)生使能信號，控制步進脈沖發(fā)生單元產(chǎn)生計數(shù)脈沖。這時運算單元開始進行累加／減計算并且計數(shù)器記錄已產(chǎn)生的脈沖個數(shù)。累加／減運算器的輸出值通過D／A變換器轉(zhuǎn)換為電壓值控制相關(guān)硬件電路。
5)當運算單元內(nèi)計數(shù)器的計數(shù)值達到本段設(shè)定的步進個數(shù)時，運算單元產(chǎn)生中斷信號通過中斷處理單元進行中斷識別并通知運算單元內(nèi)已產(chǎn)生中斷的模塊自動從RAM內(nèi)讀取下一段的初始值。運算單元內(nèi)四個模塊產(chǎn)生中斷的中斷級別各不相同，如果多個中斷同時產(chǎn)生，那么中斷處理單元會對各中斷進行緩存、排序并且首先處理中斷級別高的中斷。
6)當下一個計數(shù)脈沖到來時，運算單元內(nèi)產(chǎn)生中斷的模塊又會重新開始累加／減運算并計數(shù)，重復(fù)4、5步。
7)觸發(fā)單元記錄掃描時間。當掃描時間達到預(yù)設(shè)值時，觸發(fā)單元控制使能信號為低電平，各寄存器復(fù)位，掃描過程結(jié)束。
3 模塊內(nèi)部實現(xiàn)
1)地址譯碼／數(shù)據(jù)緩存單元地址譯碼／數(shù)據(jù)緩存單元連接外部總線，通過譯碼接收屬于本掃描控制器的數(shù)據(jù)和控制字，包括：復(fù)位控制字、掃描使能控制字、觸發(fā)單元內(nèi)計數(shù)器的計數(shù)值(用于計算掃描時間)、步進脈沖發(fā)生單元內(nèi)計數(shù)器的計數(shù)值(用于產(chǎn)生步進脈沖)以及RAM內(nèi)需存儲的控制量DAC值。
2)RAM存儲單元
存儲控制量DAC值。如果接收機內(nèi)地址資源足夠豐富，軟件可以通過地址譯碼／數(shù)據(jù)緩存單元直接訪問RAM。如果接收機內(nèi)地址資源有限，可以將整個RAM劃分為若干個區(qū)域(段地址)，每個區(qū)域?qū)?yīng)于一種控制量。每種控制量的各分段數(shù)據(jù)依次排列，可通過段內(nèi)偏移地址訪問。
3)運算單元
運算單元包括RAM數(shù)據(jù)回讀模塊、計數(shù)器及累加／減運算器模塊。RAM數(shù)據(jù)回讀模塊的回讀方式取決與RAM內(nèi)數(shù)據(jù)的存儲格式；計數(shù)器通過將讀取的步進個數(shù)值與當前的計數(shù)值進行比較決定是否產(chǎn)生中斷。在實際應(yīng)用中，累加／減運算器位數(shù)有限，而計算的步進DAC值位數(shù)有可能大大超過運算器位數(shù)，這就要求設(shè)計人員必須認真選取步進DAC的有效長度，對DAC值進行適當截取，使控制誤差能夠在可接受的范圍內(nèi)。累加／減運算器模塊在步進脈沖的觸發(fā)下，對初始值進行累加／減運算，其DAC值輸出位數(shù)等于選甩的DAC器件位數(shù)。
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